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Description
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
The VG3617161ET is CMOS Synchronous Dynamic RAM organized as 524,288-word X 16-bit X 2-bank. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V power supply. This SDRAM is delicately designed with performance concern for current high-speed application. Programmable CAS Latency and Burst Length make it possible to be used in widely various domains. It is packaged by using JEDEC standard pinouts and standard plastic 50-pin TSOP II.
Features
* Single 3.3V +/- 0.3V power supply * Clock frequency:166MHz, 143MHz, 125MHz * Fully synchronous with all signals referenced to a positive clock edge * Programmable CAS Iatency (2,3) * Programmable burst length (1,2,4,8,& Full page) * Programmable wrap sequence (Sequential/Interleave) * Automatic precharge and controlled precharge * Auto refresh and self refresh modes * Dual internal banks controlled by A11(Bank select) * Simultaneous and independent two bank operation * I/O level : LVTTL interface * Random column access in every cycle * X16 organization * Byte control by LDQM and UDQM * 4096 refresh cycles/64ms * Burst termination by burst stop and precharge command
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Pin Configuration
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
50-Pin Plastic TSOP(II)(400 mil)
VDD
DQ0 DQ1
1 2 3 4 5 6 7
50 49 48 47 46 45 44
VSS
DQ15 DQ14
VSSQ
DQ2 DQ3
VSSQ
DQ13 DQ12
VDDQ
DQ4 DQ5
VDDQ
DQ11 DQ10
VG3617161ET
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
VSSQ
DQ6 DQ7
VSSQ
DQ9 DQ8
VDDQ LDQM WE CAS RAS CS (BS)A11 A10 A0 A1 A2 A3 VDD
VDDQ NC UDQM CLK CKE NC A9 A8 A7 A6 A5 A4 VSS
Pin Description (VG3617161ET)
Pin Name A0-A11
Function Address inputs - Row address A0-A10 - Column address A0-A7 A11: Bank select Data-in/data-out Row address strobe Column address strobe Write enable Ground Power
Pin Name LDQM, UDQM
Function Lower DQ mask enable and Upper DQ mask enable
DQ0~DQ15 RAS CAS WE VSS VDD
CLK CKE CS VDDQ VSSQ
Clock input Clock enable Chip select Supply voltage for DQ Ground for DQ
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VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Block Diagram
CLK CKE
Clock Generator
Address
Mode Register
Row Decoder
Row Address Buffer & Refresh Counter
Bank B
Bank A
Sense Amplifier
Command Decoder
RAS CAS WE
Control Logic
CS
Data Control Circuit
Input & Output Buffer Page 3
Latch Circuit
Column Address Buffer & Burst Counter
Column Decoder & Latch Circuit
DQM
DQ
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Absolute Maximum Ratings(1)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Parameter Voltage on any pin relative to Vss Supply voltage relative to Vss Short circuit output current Power dissipation Operating temperature Storage temperature
Symbol VIN,VOUT VDD,VDDQ IOUT PD TOPT TSTG
Value -1.0 to +4.6 -1.0 to +4.6 50 1.0 0 to + 70 -55 to + 125
Unit V V mA W C C
Recommended DC Operating Conditions (TA=0~70C)
Parameter Supply Voltage Input High Voltage, all inputs Input Low Voltage, all inputs
Symbol VDD VIH VIL
Min 3.0 2.0 -0.3
Typ 3.3 - -
Max 3.6 VDD+0.3 0.8
Unit V V V
Note
I II
Note I.Overshoot limit : VIH(MAX.)=VDDQ+2.0V with a pulse width < 3ns II .Undershoot limit : VIL=VSSQ-2.0V with a pulse width< 3ns and -1.5V with a pulse width< 5ns DC Electrical Characteristics Parameter IIL IOL Description Input Leakage Current ( 0V VIN V DD All other pins not under test = 0V) Output Leakage Current V Output disable, ( 0V V ) OUT DDQ LVTTL Output "H" Level Voltage(lOUT = -2mA) LVTTL Output "L" Level Voltage(lOUT = 2mA) Min. -5 Max. 5 Unit A A Note
-5
5
VOH VOL
2.4 -
0.4
V V
Capacitance (TA=25C,f=1MHZ)
Parameter Input capacitance(CLK) Input capacitance(all input pins except data pins) Data input/output capacitance
Symbol C11 C12 CI/O
Typ 2.5 2.5 4.0
Max 4 5 6.5
Unit pF pF pF
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IDD Specifications (VDD = 3.3V
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
0.3V, TA = 0 ~ 70C)
-6 -7
Max Min Max Min
-8
Max
Unit Note 95 3,4
Description/test condition Operating Current , outputs open t t RC RC ( min ) Address changed once during tCK(min). Burst length = 1 (One bank active) Precharge Standby Current in non power-down mode CKE VIH (min), CS V IH (min), tCK =tCK(min) Input signals are changed once during 2 clocks Precharge Standby Current in non power-down mode CKE VIH (min), tCK = , CLK Input signals are stable Precharge Standby Current in power-down mode CKE V IL (max), tCK = tCK(min) Precharge Standby Current in power-down mode CKE V IL (max), tCK = , CLK
Symbol IDD1
Min
115
105
IDD2N
40
40
40
3
IDD2NS
35
35
35 mA
V IL (max)
IDD2P 2 2 2
VIL (max)
IDD2PS
2
2
2
Active Standby Current in non power-down mode CKE V IH (min), CS VIH(min), tCK = tCK(min) Input signals are changed once during 2 clocks Active Standby Current in non power-down mode CKE
IDD3N
50
50
50
3
V IH (min), tCK = ,
CLK
VIL (max)
IDD3NS
40
40
40
Input signals are stable Active Standby Current in power-down mode CKE V IL (max), tCK = tCK(min) Active Standby Current in power-down mode CKE IDD3P IDD3PS 35 35 35 35 35 35
V IL (max), tCK = ,
CLK
VIL (max)
Operating Current (Page burst, and all banks activated) tCCD = tCCD(min), outputs open, gapless data Refresh Current tRC tRC (min) (tREF = 64ms) Self Refresh Current CKE
IDD4
150
140
130
4,5
IDD5 IDD6
100 1
90 1
80 1
3
0.2V
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A.C Characteristics: (6)(7)(8)(10) (VDD=3.3V 0.3V , VSS=0V, Ta=0 to 70C)
Symbol A.C. Parameter Min tCH tCL tT tCK3 tCK2 tIS tIH tDS tDH tLZ tHZ3 tHZ2 tAC3 tAC2 tOH tRCD tRRD tCCD tDPL tRAS tRP tDAL3 tDAL2 tRC tRSC tREF tSRX tBDL tPDE Data output hold time RAS to CAS delay Row activate to row activate delay CAS to CAS Delay time Last data in to precharge Row activate to precharge time Precharge to refresh/row activate command Data-in to ACT (REF) Command (CL = 3) Data-in to ACT (REF) Command (CL = 2) Row cycle time Mode Register Set Cycle time Refresh time Minimum CKE "High"for Self-Refresh exit Last data in to burst STOP command Power Down Exit set-up time 1 1 1 Clock high time Clock low time Transition time (Rise and Fall) Clock cycle time CL* = 3 CL* = 2 Address/Control Input setup time Address/Control Input hold time Data Input setup time Data Input hold time Data output low impedance Data output high impedance Access time from CLK (positive edge) CL* = 3 CL* = 2 CL* = 3 CL* = 2 2.3 18 12 1 2 36 3 5 5 54 2 64 1 1 1 100,000 2.5 2.5 0.5 6 8 1.5 1 1.5 1 1 5.5 6 5.5 6 2.5 20 14 1 2 42 3 5 5 63 2 10 -6 Max Min 2.5 2.5 0.5 7 10 1.75 1 1.75 1 1 -7
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
-8 Max Min 3 3 10 0.5 8 12 2 1 2 1 1 5.5 7 6 7 2.5 20 16 1 2 6 7 6 7 10 Max
Unit
Note
ns
9 9
CLK CLK
100,000
100,000
48 3 5 5 72 2
ns CLK CLK CLK ns CLK
64 1 1 1
64
ms CLK CLK CLK
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. 2. All voltages are referenced to VSS. 3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and tRC. 4. These parameters depend on the output loading. Specified values are obtained with the outputs open. 5. Assume minimum column address update cycle tCCD (min).
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6. Power-up sequence is described in Note 10. 7. A.C. Test Conditions Reference Level of Output Signals Output Load Input Signal Levels Transition Time (Rise and Fall) of Input Signals Reference Level of Input Signals
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
1.4V Reference to the Under Output Load (B) 2.4V / 0.4V 1ns 1.4V
3.3V 1.2K
Output
Output
1.4V 50 ZO=50 30pF
30pF
870
LVTTL D.C. Test Load (A)
LVTTL A.C. Test Load (B)
8. Transition times are measured between VIH and VIL. Transition (rise and fall) of input signals are fixed slope (1 ns). 9. tHZ defines the time at which the outputs achieve the open circuit condition and are not reference levels.
10. Power up sequence Power up must be performed in the following sequence. 1) Power must be applied to VDD and VDDQ (simultaneously) when all input signals are held "NOP" state and CKE = "H", DQM = "H". The CLK signals must be started at the same time. 2) After power-up, a pause of 200u secouds minimum is required. Then, it is recommended that DQM is held "high" (VDD levels) to ensure DQ output to be in the high impedance. 3) Both banks must be precharged. 4) Mode Register Set command must be asserted to initialize the Mode Register. 5) A minimum of 8 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the device. Sequence of 4 and 5 may be changed.
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Basic Features and Function description 1.Simplified State Diagram
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Self
Refresh
try en
LF SE
Mode Register Set
MRS
IDLE
LF SE
it ex
REF
AUTO Refresh
CK E
KE C
ROW ACTIVE
BS T
ACT
Power Down
CKE CKE
T BS
Active Power Down
ad Re
W r it e
Au Write to p red with har ge
h wit rge ad cha Re Pre to Au
Write
Read
PRE
WRITE SUSPEND
CKE CKE
WRITE
Read
READ
CKE CKE
READ SUSPEND
Write
AutoRead w Pre ith cha rge
h rec E(P PR
Write with Auto Precharge
ith e d w arg Rea Prech o Aut
m in atio n)
Read with Auto Precharge
ter
WRITE A SUSPEND
CKE CKE
WRITE A
CKE READ A CKE
READ A SUSPEND
POWER ON
Precharge
Precharge
Automatic sequence Manual input Note: After the AUTO refresh operation, precharge operation is performed automatically and enter the IDLE state
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2.Truth Table 2.1 Command Truth Table
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
FUNCTION Device deselect No operation Mode register set Bank activate Read Read with auto precharge Write Write with auto precharge Precharge select bank Precharge all banks Burst stop
Symbol DESL NOP MRS ACT READ READA WRIT WRITA PRE PALL BST
CKE n-1 H H H H H H H H H H H
n X X X X X X X X X X X
CS H L L L L L L L L L L
RAS X H L L H H H H L L H
CAS X H L H L L L L H H H
WE X H L H H H L L L L L
A11 X X L BS(2) BS(2) BS(2) BS(2) BS(2) BS(2) X X
A10 X X L Row L H L H L H X
A9A0 X X V Row Col(1) Col(1) Col(1) Col(1) X X X
Note: (1) Column address: A0~A7 (2) BS: Bank Select. L means Bank A and H means Bank B. 2.2 DQM Truth Table
CKE FUNCTION Data write/output enable Data mask/output disable Upper byte write enable/output enable Lower byte write enable/output enable Upper byte write inhibit/output disable Lower byte inhibit/output disable Symbol ENB MASK ENBU ENBL MASKU MASKL n-1 H H H H H H n-1 X X X X X X
DQM UDQM LDQM L H L X X L H X X H
2.3 CKE Truth Table
Current State Activating Any Clock suspend Idle Idle Self refresh Idle Power down
Function Clock suspend mode entry Clock suspend Clock suspend mode exit CBR refresh command Self refresh entry Self refresh exit Power down entry Power down exit
Symbol
REF SELF
CKE n-1 n H L L L L H H H H L L H L H H L L H
CS X X X L L L H X X
RAS X X X L L H X X X
CAS X X X L L H X X X
WE X X X H H H X X X
Address X X X X X X X X X
H : High level, L : Low level, X : high or Low level(Don' care), V : Valid Data input t
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2.4 Operative Command Table
Current state Idle CS H L L L L L L L Row active H L L L L L L L Read H L L L L L L L L Write H L L L L L L L L RAS X H H H L L L L X H H H L L L L X H H H H L L L L X H H H H L L L L CAS X H L L H H L L X H L L H H L L X H H L L H H L L X H H L L H H L L WE X X H L H L H L X X H L H L H L X H L H L H L H L X H L H L H L H L X X BA,CA,A10 BA,CA,A10 BR,RA BA,A10 X Op-Code X X BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X Op-Code X X X BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X Op-Code X X X BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X Op-Code Address Command DESL NOP or BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MPS DESL NOP or BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
(1/3)
Action Nop or Power down Nop or Power down ILLEGAL ILLEGAL Row active Nop Refresh or Self refresh Mode register access Nop Nop Begin read:Determine AP Begin write:Determine AP ILLEGAL Precharge ILLEGAL ILLEGAL Continue burst to end Row active Continue burst to end Row active Burst stop Row active Term burst, new read:Determine AP Term burst, start write:Determine AP ILLEGAL Term burst,precharging ILLEGAL ILLEGAL Continue burst to end write recovering Continue burst to end Write recovering Burst stop Row active Term burst, start read: determine AP Term burst, new write:Determine AP ILLEGAL Term burst precharging ILLEGAL ILLEGAL
Notes 2 2 3 3
4
5 5 3 6
7 7,8 3
7,8 7 3 9
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Current state Read with auto precharge CS H L L L L L L L L Write with auto precharge H RAS X H H H H L L L L X CA X H H L L H H L L X WE X H L H L H L H L X Address X X X BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X Op-Code X Command DESL NOP BST
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
(2/3)
Action Continue burst to end Prech arg ing Continue burst to end Prech arg ing ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst to end Write recovering with auto precharge Continue burst to end Write recovering with auto precharge ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop Enter idle after tRP Nop Enter idle after tRP Nop Enter idle after tRP ILLEGAL ILLEGAL ILLEGAL Nop Enter idle after tRP ILLEGAL ILLEGAL Nop Enter row active after tRCD Nop Enter row active after tRCD Nop Enter row active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Notes
READ/READA WRIT/WRITA ACT PRE/PALL PEF/SELF MRS DESL
3 3
L
H
H
H
X
NOP
L L L L L L L Precharging H L L L L L L L L Row activating H L L L L L L L L
H H H L L L L X H H H H L L L L X H H H H L L L L
H L L H H L L X H H L L H H L L X H H L L H H L L
L H L H L H L X H L H L H L H L X H L H L H L H L
X BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X Op-code X X X BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X Op-Code X X X BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X Op-Code
BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS
3 3
3 3 3
3 3 3,10 3
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Current state Write recovering CS H L L L L L L L L Write recovering with auto precharge H L L L L L L L L Refreshing H L L L L Mode register accessing H L L L L RAS X H H H H L L L L X H H H H L L L L X H H L L X H H H L CA X H H L L H H L L X H H L L H H L L X H L H L X H H L X WE X H L H L H L H L X H L H L H L H L X X X X X X H L X X Address X X X BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X Op-Code X X X BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X Op-Code X X X X X X X X X X Command DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL PEF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT REF/PALL REF/SELF MRS DESL NOP/BST READ/WRIT
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
(3/3)
Action
Nop Enter row active after tDPL Nop Enter row active after tDPL Nop Enter row active after tDPL
Notes
Start read, Determine AP New write, Determine AP ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Nop Enter precharge after tDPL Nop Enter precharge after tDPL Nop Enter precharge after t DPL
8
3 3
ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Nop Enter idle after tRC Nop Enter idle after tRC
3,8 3 3 3
ILLEGAL ILLEGAL ILLEGAL
Nop Enter idle after 2 Clocks Nop Enter idle after 2 Clocks
ACT/PRE/PALL REF/SELF/MRS DESL NOP BST READ/WRITE ACT/PRE/PALL/ REF/SELF/MRS
ILLEGAL ILLEGAL ILLEGAL
Note 1. All entries assume that CKE was active (High level)during the preceding clock cycle. 2. If both banks are idle, and CKE is inactive(Low level), the device will enter Power down mode. All input buffers except CKE will be disabled. 3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. 4. If both banks are idle, and CKE is inactive(Low level), the device will enter Self refresh mode. All input buffers except CKE will be disabled. 5. IIIegal if tRCD is not satisfied. 6. IIIegal if tRAS is not satisfied. 7. Must satisfy burst interrupt condition. 8. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. Must mask preceding data if tDPL is not satisfied. 10. IIIegal if tRRD is not satisfied.
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2.5 Command Truth Table for CKE Current state Self refresh (SR)
CKE n-1 H L L L L L H H H H H H H H L L H L L H H H H H H H H H H L H H L L RAS n X H H H H L H H H H L L L L H L X H L H H H H H L L L L L X H L H L CS X H L L L X H L L L H L L L X X X X X H L L L L H L L L L X X X X X RAS X X H H L X X H H L X H H L X X X X X X H L L L X H L L L X X X X X
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
CAS X X H L X X X H L X X H L X X X X X X X X H L L X X H L L X X X X X
WE X X X X X X X X X X X X X X X X X X X X X X H L X X X H L X X X X X
Address X X X X X X X X X X X X X X X X X X
Action INVALID,CLK(n-1)would exit S.R. SR Recovery SR Recovery ILLEGAL ILLEGAL Maintain S.R. Idle after tRC Idle after tRC ILLEGAL ILLEGAL Begin clock suspend next cycle Begin clock suspend next cycle ILLEGAL ILLEGAL Exit clock suspend next cycle Maintain clock suspend INVALID, CLK(n-1) would exit P.D. EXIT PD Idle Maintain power down mode Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operation in Operative Command Table Refresh Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table Self refresh Refer to operations in Operative Command Table Power down Refer to operations in Operative Command Table Begin clock suspend next cycle Exit clock suspend next cycle Maintain clock suspend
Notes
2 2 2 2
Self refresh recovery
5 5
2
Power down (PD)
2
Both banks idle
X OpCode
X OpCode X X X X X
3
3
Any state other than listed above
4
Note 1. H : Hight level, L : low level, X : High or low level(Don't care). 2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. 3. Power down and Self refresh can be entered only from the both banks idle state. 4. Must be legal command as defined in Operative Command Table. 5 .IIIegal if tSRX is not satisfied.
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VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
3.Initiallization The synchronous DRAM is initialized in the power on sequence. Once power has been applied, a 200us minimum delay is needed in which stable power and input signals are maintained. During this delay, CKE and DQM recommend to be held high. After the 200us delay, both banks must be precharged using the precharge command. Once precharge is completed and the minimum tRP is satisfied, the mode register can be programmed. Minimum 8 CBR refresh cycles must be performed before or after the mode register set command. 4.Programming the Mode Register The mode register is programmed by the mode register set command using address bits A11 through A0 as data inputs. The register retains data until it is reprogrammed or until the device loses power. The mode register has four fields; Options CAS latency Wrap type Burst length : A11 through A7 : A6 through A4 : A3 : A2 through A0
Following mode register programming, no command can be asserted befor at least two clock cycles have elapsed. CAS Latency CAS latency is the most critical parameter to be set. It tells the device how many clocks must elapse before the data will be available. The SDRAM is capable of reconfiguring its internal architecture based on the value of CAS latency. The value is determined by the frequency of the clock and the speed grade of the device. The value can be programmed as 2 or 3. Burst Length Burst Length is the number of words that will be output or input in read or write cycle. After a read burst is completed, the output bus will become high impedance. The burst length is programmable as 1,2,4,8 or full page. Wrap Type (Burst Sequence) The wrap type specifies the order in which the burst data will be addressed. The order is programmable as either "Sequential" or "Interleave". The method chosen will depend on the type of CPU in the system. Some microprocessor cache systems are optimized for sequential addressing and others for interleaved addressing. Both sequences support bursts of 1,2,4 and 8. Only the sequential burst. supports the full-page length.
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5.Mode Register
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
11 0 11 0
10 0 10 0
9 1 9 0
8 0 8 0
7 0 7 0
6 6
5 4 LTMODE 5 4 LTMODE
3 2 WT 3 2 WT
1 BL 1 BL
0 0 Burst Read and Single Write X=Don' care t Mode Register Set Bits2-0 000 001 010 Burst length 011 100 101 110 111 Wrap type 0 1 WT=0 1
2 4 8 R R R
Full page
WT=1 1
2 4 8 R R R R
Sequential Interleave
Bits6-4 000 001 010 Latency mode 011 100 101 110 111
Remark R:Reserved
CAS Iatency R
R 2 3 R R R
R
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5.1 Burst Length and Sequence (Burst Length= 2) Starting Address (column address A0, binary) 0 1 (Burst Length=4) Starting Address (column address A1-A0, binary) 00 01 10 11 (Burst Length=8) Starting Address (column address A2-A0, binary) 000 001 010 011 100 101 110 111 Sequential Addressing Sequence (decimal) 0,1,2,3,4,5,6,7 1,2,3,4,5,6,7,0 2,3,4,5,6,7,0,1 3,4,5,6,7,0,1,2 4,5,6,7,0,1,2,3 5,6,7,0,1,2,3,4 6,7,0,1,2,3,4,5 7,0,1,2,3,4,5,6 Sequential Addressing Sequence (decimal) 0,1,2,3 1,2,3,0 2,3,0,1 3,0,1,2 Sequential Addressing Sequence (decimal) 0,1 1,0
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Interleave Addressing Sequence(decimal) 0,1 1,0
Interleave Addressing Sequence(decimal) 0,1,2,3 1,0,3,2 2,3,0,1 3,2,1,0
Interl eave Addressing Sequence(decimal) 0,1,2,3,4,5,6,7 1,0,3,2,5,4,7,6 2,3,0,1,6,7,4,5 3,2,1,0,7,6,5,4 4,5,6,7,0,1,2,3 5,4,7,6,1,0,3,2 6,7,4,5,2,3,0,1 7,6,5,4,3,2,1,0
Full page burst is an extension of the above tables of sequential addressing, with the length being 256 words.
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6.Address Bits of Bank-Select and Precharge Row A0 A1 A2 A3 A4 A5 A6 (Activate command) A7 A8 A9 A10 A11
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
0 Select Bank A "Activate" command 1 Select Bank B "Activate" command
Row A0 A1 A2 A3 A4 A5 A6 (Precharge)
A7 A8 A9 A10 A11 A10 A11 Result 0 0 1 0 1 x Precharge Bank A Precharge Bank B Precharge All Banks
x:Don' care t
0 1
Disable Auto-Precharge (End of Burst) Enable Auto-Precharge (End of Burst)
Col. A0 A1 A2 A3 A4 A5 A6 (CAS strobes)
A7 A8 A9 A10 A11
0 Enable Read/Write commands for Bank A 1 Enable Read/Write commands for Bank B
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7.PRECHARGE
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
The PRECHARGE command can be asserted anytime after tRAS(min) is satisfied. Soon after the PRECHARGE command is asserted, PRECHARGE operation is performed. The synchronous DRAM enters the idle state after tRP(min) is satisfied. The parameter tRP is the time required to perform the PRECHARGE. The earliest timing in a READ cycle that a PRECHARGE command can be asserted without losing any data in the burst is as followed. PRECHARGE
Burst lengh=4 T0 T1 T2 T3 T4 T5 T6 T7
CLK
Command
Read
PRE
CAS latency=2 DQ Hi-Z Q0 Q1 Q2 Q3
Command CAS latency=3 DQ
Read
PRE
Hi-Z Q0 Q1 Q2 Q3
CAS latency= 2: One clock earlier than the last output data. 3: Two clocks earlier than the last output data.
(tRAS is satisfied)
In order to write all data to the memory cell correctly, the asynchronous parameter"tDPL" must be satisfied. The t DPL(MIN.) specification defines the earliest time that a PRECHARGE command can be asserted after a WRITE cycle. The minimum number of clocks are calculated by dividing tDPL(min.) by the clock cycle time. In summary, the PRECHARGE command can be asserted relative to the reference clock of the last valid data. In the following table, minus means clocks before the reference, plus means time after the reference.
CAS latency 2 3
READ -1 -2
WRITE +tDPL(min.) +tDPL(min)
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8.AUTO PRECHARGE
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
During a READ or WRITE command cycle, A10 controls whether AUTO PRECHARGE is selected. If A10 is high in the READ or WRITE command (READ with AUTO PRECHARGE command or WRITE with AUTO PRECHARGE command), AUTO PRECHARGE is selected and precharging begins automatically after the burst access. In the WRITE cycle, tDAL(min.) must be satisfied to assert the next active command to the bank being precharged. When using AUTO PRECHARGE in the READ cycle, knowing when the PRECHARGE starts is important because the tRAS must be satisfied. Once AUTO PRECHARGE has started, an active command to the bank can be asserted after tRP(min.) has been satisfied. The timing at which the AUTO PRECHARGE cycle begins depends both on the CAS Iatency programmed into the mode register and on whether the cycle is READ or WRITE. 8.1 READ with AUTO PRECHARGE During a READA cycle, the AUTO PRECHARGE begins one clock earlier(CAS Iatency of 2) or two clocks earlier(CAS Iatency of 3) than the last data word output.
READ with AUTO PRECHARGE
Burst lengh=4 T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK
Command
READA B Auto precharge starts
CAS latency=2 DQ Hi-Z
QB0
QB1
QB2
QB3
Command
READA B Auto precharge starts
CAS latency=3 DQ Hi-Z QB3
QB0
QB1
QB2
Remark: READA means READ with AUTO PRECHARGE
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8.2 WRITE with AUTO PRECHARGE the device WRITE with AUTO PRECHRGE
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
During a WRITA cycle, the AUTO PRECHARGE starts at tDPL(min.) after the last data word input to
Burst lengh=4 T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK
Command
WRITA B
AUTO PRECHARGE starts tDPL
CAS latency=2
DQ
DB0
DB1
DB2
DB3
Hi-Z_
Command
WRITA B
AUTO PRECHARGE starts tDPL
CAS latency=3
DQ
DB0
DB1
DB2
DB3
Hi-Z_
Remark WRITA means WRITE with AUTO PRECHARGE
In summary, the auto precharge cycle begins relative to a reference clock that indicates the last data word is valid. In the table below, minus means clocks before the reference; plus means clocks after the reference.
CAS latency 2 3
READ -1 -2
WRITE +tDPL(min.) +tDPL(min)
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9.READ/WRITE Command Interval 9.1 READ to READ command interval
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
When a new READ command is asserted during a READ cycle, it will be effective after the CAS latency, even if the previous READ operation has not completed. READ will be interrupted by another READ. A READ command can be asserted in every clock without restriction. READ to READ Command Interval
Burst lengh=4, CAS latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK Read A Read B
Command
DQ
QA0
QB0
QB1
QB2
QB3
Hi-Z_
1 cycle
9.2 WRITE to WRITE Command Interval When a new WRITE command is asserted during a WRITE cycle, the previous burst will be terminated and the new burst will begin with the new WRITE command. WRITE will be interrupted by another WRITE. A WRITE command can be asserted in every clock without restriction.
WRITE to WRITE Command Interval
Burst lengh=4, CAS latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK Write A Write B
Command
DQ
QA0
QB0
QB1
QB2
QB3
Hi-Z_
1 cycle
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WRITE to READ Command Interval
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
9.3 WRITE to READ Command Interval The WRITE command to READ command interval is a minimum of 1 cycle. Only the WRITE data preceding the READ command will be written. The data bus must be in high-impedance at least one cycle prior to the first DOUT.
Burst lengh=4 T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK 1 cycle Command CAS latency=2 Hi-Z WRITE A Read B
DQ
DA0
QB0
QB1
QB2
QB3
Command
Write A
Read B
CAS latency=3 DQ DA0 Hi-Z QB0 QB1 QB2 QB3
9.4 READ to WRITE Command Interval During READ cycle, READ can be interrupted by WRITE. The data bus must be in high-impedance using DQM before the WRITE command. DQM must be high at least 3 clocks prior to the WRITE command. This restriction is necessary to avoid a data bus conflict.
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READ to WRITE Command Interval
T0 T1 T2 T3 T4
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
T5
T6
T7
CAS latency=2 T8
CLK
Command
Read
Write
DQM
DQ
Hi-Z
D0
D1
D2
D3
1 cycle
T0
T1
T2
T3
T4
T5
T6
T7
Burst length=8, CAS latency=2 T8 T9
CLK
Command
Read
Write
DQM
DQ
Q0
Q1
Q2 Hi-Z is necessary
D0
D1
D2
example: Burst length=4, CAS latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK
Command
Read
Write
DQM
DQ
Q2
Hi-Z is necessary
D0
D1
D2
The minimum command interval = (4+1) cycles
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10.1 BURST STOP Command
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
10.BURST TERMINATION There are two methods to terminate a BURST operation other than using a READ or a WRITE command. One is the BURST STOP command and the other is the PRECHARGE command.
During a READ BURST. when the BURST STOP command is asserted, the BURST READ outputs are terminated and the data bus goes to high-impedance after the CAS latency from the BURST STOP command. During a WRITE BURST. when the BURST STOP command is asserted, any data provided at that cycle will not be written. The BURST WRITE is effectively terminated and no further data can be written until a new WRITE command is asserted. Burst Termination
T0 T1 T2 T3 T4 T5 Burst lengh=X, CAS Intency=2,3 T7 T6
CLK BST
Command
Read
CAS latency=1 DQ
Q0
Q1
Q2
Hi-Z
CAS latency=2 DQ
Q0
Q1
Q2
Hi-Z
CAS latency=3 DQ
Q0
Q1
Q2
Hi-Z
Remark BST: Burst stop command
Burst lengh=X, CAS latency=1,2,3 T7 T6
T0
T1
T2
T3
T4
T5
CLK BST
Command
Write
CAS latency=1,2,3 Q0 DQ Q0 Q1 Q2 Hi-Z_
Remark BST: Burst stop command
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10.2 PRECHARGE TERMINATION 10.2.1 PRECHARGE TERMINATION in READ Cycle
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
During a READ cycle, the BURST READ operation can be terminated by a PRECHARGE command. When the PRECHARGE command is asserted, the BURST READ operation is terminated and PRECHARGE starts. Read data will remain valid until zero clock(CAS latency of 1), one clock(CAS latency of 2)or two clocks(CAS latency of 3) after the PRECHARGE command and the same bank can be activated again after tRP(min) from the PRECHARGE command.
PRECHARGE TERMINATION in READ Cycle
T0 T1 T3 T6 Burst lengh= X T8
T2
T4
T5
T7
CLK Command Read PRE tRP CAS latency=1 DQ Q0 Q1 Q2 Q3 tRP Hi-Z ACT
Command
Read
PRE
ACT
CAS latency=2 DQ Q0 Q1 Q2 Q3 tRP command Read PRE tRP Hi-Z ACT Hi-Z
CAS latency=3 DQ
Q0
Q1
Q2
Q3
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10.2.2 PRECHARGE TERMINATION in WRITE Cycle
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
During a WRITE cycle, the BURST WRITE operation can be terminated by a PRECHARGE command. when the PRECHARGE command is asserted, the BURST WRITE operation in immediately terminated and PRECHARGE starts. The same bank can be activated again after tRP(min.) from the PRECHARGE command. The DQM must be high to mask invalid data in. When CAS latency is 1, 2 or 3, the data written prior to the PRECHARGE command will be correctly stored. However, invalid data may be written at the same clock as the PRECHARGE command. To prevent this from happening, DQM must be high at the same clock as the PRECHARGE command. This will mask the invalid data.
PRECHARGE TERMINATION in WRITE Cycle
T0 T1 T2 T3 T4 T5 T6 T7 Burst lengh = X T8
CLK PRE tRP CAS latency=1 DQM DQ D0 D1 D2 D3 D4 tRP Write PRE ACT Hi-Z ACT
Command
Write
Command
CAS latency=2 DQM DQ D0 D1 D2 D3 D4 tRP command Write PRE ACT Hi-Z
CAS latency=3 DQM Hi-Z
DQ
D0
D1
D2
D3
D4
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VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Timing Diagram
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Mode Register Set
T0 T1 T2 T3 T4 T5
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
T6
T7
T8
T9
T10
CLK
CKE
t
RSC
CS
RAS
CAS
WE
A11(BS)
A10
A0-A9
Key
DQM
t
DQ Hi-Z
RP
Precharge Command All Banks
Mode Register Set Command
Command
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AC Parameters for Write Timing (1 of 2)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5
T6 T7 T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CH t CL t CMS t CMH t CK2 Begin Auto Precharge Begin Auto Precharge Bank A Bank B (Bank D)
CKE
t CKS
t CKH
CS
RAS
CAS
WE
BS
A10
t AS tAH
ADD
DQM
tRCD
DQ
t RRD tRC
tDAL
tDS t DH t DPL t RP
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3
Activate Write with Command Auto Precharge Bank A Command Bank A
Write with Activate Activate Command Auto Precharge Command Command Bank A Bank B (Bank D) Bank B (Bank D)
Write without Auto Precharge Command Bank A
Precharge Command Bank A
Activate Command Bank A
Activate Command Bank B (Bank D)
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AC Parameters for Write Timing (2 of 2)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CLK
t CL t CH t CK3 t CMS t CMH Begin Auto Precharge Begin Auto Precharge Bank A Bank B (Bank D) t CKH
CKE
t CKS
CS
RAS
CAS
WE
BS
A10
t AS t AH
ADD
DQM
tRCD
DQ
t RRD
t
tDAL RC
tDS t DH t DPL t RP
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3
QAb0 QAb1 QAb2 QAb3
Activate Command Bank A
Write with Activate Write with Auto Precharge Command Auto Precharge Command Bank B Command Bank A Bank B (Bank D) (Bank D)
Activate Command Bank A
Write without Auto Precharge Command Bank A
Precharge Command Bank A
Activate Command Bank A
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AC Parameters for Read Timing (1 of 2)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=2, CAS Latency=2
T0 CLK
tCH tCL
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
tCK2 tCMS tCMH Begin Auto Precharge Bank B t CKH
CKE
tCKS
CS
RAS
CAS
WE
A11(BS)
A10
RAa tAS tAH
RBa
RAb
A0-A9
RAa
CAa tRRD
RBa
CBa
RAb
tRAS tRC
DQM
tAC2 tLZ tAC2 tOH QAa0 tHZ tOH QAa1 QBa0
t RCD
tRP tHZ QBa1
DQ
Hi-Z
Activate Command Bank A
Read Command Bank A
Activate Command Bank B
Read with Auto Precharge Bank B
Precharge Command Bank A
Activate Command Bank A
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AC Parameters for Read Timing (2 of 2)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=2, CAS Latency=3
T10 T11 T12
T13 T14 T15
tt CH CL
t CK3 t CMS t CMH Begin Auto Precharge Bank B
CKE
t CKS
t CKH
CS
RAS
CAS
WE
A11(BS)
A10
RAa t AH t AS
RBa
RAb
A0-A9
RAa t RRD
CAa
RBa
CBa
RAb
t RAS t RC
t RP
DQM
t RCD
tAC3 tLZ
tAC3 tOH
tHZ tOH
QAa1 QBa0
t
HZ
DQ
Hi-Z
QAa0
QBa1
Activate Command Bank A
Read Command Bank A
Activate Command Bank B
Read with Auto Precharge Command Bank B
Precharge Command Bank A
Activate Command Bank A
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Power on Sequence and Auto Refresh (CBR)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
High level is required t RSC Minimum of 8 Refresh Cycles are required
CKE
CS
RAS
CAS
WE
A11(BS)
A10
Address Key
A0~A9
DQM
High Level is Necessary t RP t
RC
DQ
Inputs Precharge 1st Auto must Command Refresh be stable All Banks Command for 200us
2nd Auto Refresh Command
Mode Command Register Set Command
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Clock Suspension During Burst Read (Using CKE) (1 of 2)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
CAa
DQM DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3
t HZ
Activate Command Bank A
Read Command Bank A
Clock Suspended 1 Cycle
Clock Suspended 2 Cycles
Clock Suspended 3 Cycles
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Clock Suspension During Burst Read (Using CKE) (2 of 2)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
CAa
DQM
t HZ
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3
Activate Command Bank A
Read Command Bank A
Clock Suspended 1 Cycle
Clock Suspended 2 Cycles
Clock Suspended 3 Cycles
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Clock Suspension During burst Write (Using CKE) (1 of 2)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
CAa
DQM DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3
Activate Command Bank A
Clock Suspended 1 Cycle Write Command Bank A
Clock Suspended 2 Cycles
Clock Suspended 3 Cycles
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Clock suspension during Burst write (Using CKE) (2 of 2)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
CAa
DQM
t
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3
Activate Command Bank A
Clock Suspended 1 Cycle Write Command Bank A
Clock Suspended 2 Cycles
Clock Suspended 3 Cycles
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Power Down Mode and Clock Mask
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
t t CKS
CKH
t CKS
CKE
VALID
CS
RAS
CAS
WE
BS
A10
RAa
A0~A9
RAa
CAa
DQM DQ
Hi-Z
QAa0 QAa1 QAa2
t
HZ
QAa3
Activate Command Bank A
ACTIVE STANDBY
Read Command Bank A Clock Mask Start Clock Mask End
Precharge Command Power Down Mode Entry
Precharge Standby
Power Down Mode Entry
Power Down Mode Exit
Power Down Mode Exit Command
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Auto Refresh (CBR)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK2
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
BS
A10
RAa
ADD
RAa
CAa
DQM
t RP t RC t RC
Q0 Q1 Q2 Q3
DQ
Hi-Z
Precharge CBR Refresh Command Command All Banks
CBR Refresh Command
Activate Write Command Command
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Self Refresh (Entry and Exit)
CLK can be Stopped*
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 CLK
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t SRX
t SRX
t CKS
CKE
t CKS
CS
RAS
CAS
WE
BS
A10
ADD
t RC t RC
DQM
DQ
Hi-Z
All Banks must be idle
Self refresh Entry
Self Refresh Exit
Self Refresh Entry Self Refresh Exit
Activate Command
* Clock can be stopped at CKE=Low. If clock is stopped, it must be restarted/stable for 4 clock cycles before CKE=High
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Random Column Read (Page Within same Bank)(1 of 2)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
RAa RAd
A0~A9
RAa
CAa
CAb
CAc
RAd
CAd
DQM DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QAb0 QAb1 QAc0 QAc1 QAc2 QAc3
QAd0 QAd1 QAd2 QAd3
Active Command Bank A
Read Command Bank A
Read Read Command Command Bank A Bank A
Precharge Activate Read Command Command Command Bank A Bank A Bank A
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Random Column Read (Page Within same Bank)(2 of 2)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
RAd
A0~A9
RAa
CAa
CAb
CAc
RAd
CAd
DQM DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QAb0 QAb1 QAc0 QAc1 QAc2 QAc3
Activate Command Bank A
Read Command Bank A
Read Read Command Command Bank A Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
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Random Column Write (Page Within same Bank) (1 of 2)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
RAd
A0~A9
RBa
CBa
CBb
CBc
RBd
CBd
DQM DQ
Hi-Z
DBa0 DBa1 DBa2 DBa3 DBb0 DBb1 DBc0 DBc1 DBc2 DBc3
DBd0 DBd1 DBd2 DBd3
Activate Command Bank B
Write Command Bank B
Write Write Command Command Bank B Bank B
Precharge Activate Write Command Command Command Bank B Bank B Bank B
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Random Column Write (Page Within same Bank) (2 of 2)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RBa
RBd
A0~A9
RBa
CBa
CBb
CBc
CBd
RBd
DQM DQ
Hi-Z
DBa0 DBa1 DBa2 DBa3 DBb0 DBb1 DBc0 DBc1 DBc2 DBc3
DBd0 DBd1 DBd2
Activate Command Bank B
Write Command Bank B
Write Command Bank B
Write Command Bank B
Precharge Command Bank B
Activate Command Bank B
Write Command Bank B
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Random Row Read (Interleaving Banks) (1 of 2)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=8, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
High
t CK2
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RBa
RAa
RBb
A0~A9
RBa
CBa
RAa
CAa
RBb
CBb
t
t RCD
AC2
t RP
DQM DQ
Hi-Z
QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7
QBb0 QBb1
Activate Command Bank B
Read Command Bank B
Activate Command Bank A
Precharge Active Command Command Bank B Bank B Read Command Bank A
Read Command Bank B
Document:1G5-0189
Rev.1
Page 45
VIS
Random Row Read (Interleaving Banks) (2 of 2)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=8, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3 High
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RBa
RAa
RBb
A0~A9
RBa
CBa
RAa
CAa
RBb
CBb
t
RCD
t AC3
t
RP
DQM DQ
Hi-Z
QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QBb0
Activate Command Bank B
Read Command Bank B
Activate Command Bank A
Read Command Bank A
Precharge Command Bank B
Activate Command Bank B
Read Precharge Command Command Bank B Bank B
Document:1G5-0189
Rev.1
Page 46
VIS
Random Row Write (Interleaving Banks) (1 of 2)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=8, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
High
t CK2
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
RBa
RAb
A0~A9
RAa
CAa
RBa
CBa
RAb
CAb
t
DQM DQ
Hi-Z
RCD
t DPL
t RP
t
DPL
QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 DAb0 DAb1 DAb2 DAb3 DAb4
Activate Command Bank A
Write Command Bank A
Activate Command Bank B
Precharge Active Command Command Bank A Bank A Write Command Bank B
Write Command Bank A Precharge Command Bank B
Document:1G5-0189
Rev.1
Page 47
VIS
Random Row Write (Interleaving Banks) (2 of 2)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=8, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
High
t CK3
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
RBa
RAb
A0~A9
RAa
CAa
RBa
CBa
RAb
CAb
t
DQM DQ
Hi-Z
RCD
t DPL
t
RP
t DPL
DAa0 DAa1 DAa2 DAa3 DAa4 DAa5 DAa6 DAa7 DBa0 DBa1 DBa2 DBa3 DBa4 QBa5 DBa6 DBb7 DAb0 DAb1 DAb2 DAb3
Activate Command Bank A
Write Command Bank A
Activate Command Bank B
Write Command Bank B
Precharge Command Bank A
Activate Command Bank A
Precharge Write Command Command Bank B Bank A
Document:1G5-0189
Rev.1
Page 48
VIS
Read and Write Cycle (1 of 2)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
CAa
CAb
CAc
DQM DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3
DAb0 DAb1
DAb3
QAc0 QAc1
QAc3
Activate Command Bank A
Read Command Bank A
The Write Data Write Command is Masked with a Bank A Zero Clock latency
Read Command Bank A
The Read Data is Masked with Two Clocks Latency
Document:1G5-0189
Rev.1
Page 49
VIS
Read and Write Cycle (2 of 2)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
CAa
CAb
CAc
DQM DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3
DAb0 DAb1
DAb3
QAc0 QAc1
QAc3
Activate Command Bank A
Read Command Bank A
Write The Write Data Read Command is Masked with a Command Bank A Bank A Zero Clock
latency
The Read Data is Masked with Two Clock Latency
Document:1G5-0189
Rev.1
Page 50
VIS
Interleaved Column Read Cycle (1 of 2)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
RBa
A0~A9
RAa
CAa
RBa
CBa
CBb
CBc
CAb
CBd
DQM
t RCD
t
AC2
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBb0 QBb1 QBc0 QBc1 QAb0 QAb1 QBd0 QBd1 QBd2 QBd3
Activate Command Bank A
Read Read Read Activate Read Read Read Command Command Command Command Command Command Command Bank A Bank A Bank B Bank B Bank B Bank B Bank B Precharge Command Bank A
Precharge Command Bank B
Document:1G5-0189
Rev.1
Page 51
VIS
Interleaved Column Read Cycle (2 of 2)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
RBa
A0~A9
RAa
CAa
RBa
CBa
CBb
CBc
CAb
DQM
t RCD t RRD t AC3
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBb0 QBb1 QBc0 QBc1 QAb0 QAb1 QAb2 QAb3
Activate Command Bank A
Read Command Bank A Activate Command Bank B
Read Read Read Read Precharge Precharge Command Command Command Command Command Command Bank A Bank B Bank B Bank B Bank B Bank A
Document:1G5-0189
Rev.1
Page 52
VIS
Interleaved Column Write Cycle (1 of 2)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
RBa
A0~A9
RAa
CAa
RBa
CBa
CBb
CBc
CAb
CBd
t RCD
t RP
t DPL
DQM
t Hi-Z
DAa0 DAa1 DAa2 DAa3 DBa0 DBa1 DBb0 DBb1 DBc0 DBc1 DAb0 DAb1 DBd0 DBd1 DBd2 DBd3
RRD
DQ
Activate Write Write Write Write Write Activate Command Command Command Command Command Command Command Bank B Bank B Bank A Bank A Bank B Bank B Bank A
Precharge Command Bank A Write Command Bank B
Precharge Command Bank B
Document:1G5-0189
Rev.1
Page 53
VIS
Interleaved Column Write Cycle (2 of 2)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
RBa
A0~A9
RAa
CAa
RBa
CBa
CBb
CBc
CAb
CBd
t RCD
t DPL
t DPL
DQM
t Hi-Z
DAa0 DAa1 DAa2 DAa3 DBa0 DBa1 DBb0 DBb1 DBc0 DBc1 DAb0 DAb1 DAd0 QAd1 QAd2 QAd3
RRD
t RP
DQ
Activate Command Bank A
Write Command Bank A Activate Command Bank B
Write Write Write Write Write Command Command Command Command Command Bank A Bank B Bank B Bank B Bank B Precharge Command Bank A
Precharge Command Bank B
Document:1G5-0189
Rev.1
Page 54
VIS
Auto Precharge after Read Burst (1 of 2)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
High
t
CK2
Start Auto Precharge Bank B Start Auto Precharge Bank A Start Auto Precharge Bank B
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
RBa
RBb
RAc
A0~A9
RAa
CAa
RBa
CBa
CAb
RBb
CBb
RAc
CAc
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QAc2
Activate Read Activate Read with Command Command Command Auto Precharge Bank A Bank A Bank B Command Bank A
Read with Activate Activate Auto Precharge Command Command Command Bank B Read with Bank A Bank A Auto Precharge Command Read with Bank B Auto Precharge Command Bank A
Document:1G5-0189
Rev.1
Page 55
VIS
Auto Precharge after Read Burst (2 of 2)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
High
t
CK3
Start Auto Precharge Bank B Start Auto Precharge Bank A Start Auto Precharge Bank B
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
RBa
RBb
A0~A9
RAa
CAa
RBa
CBa
CAb
RBb
CBb
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 QBb0 QBb1 QBb2 QBb3
Activate Command Bank A
Read Command Bank A Activate Command Bank B
Read with Auto Precharge Command Bank B
Read with Read with Auto Precharge Auto Precharge Command Command Bank A Bank B Activate Command Bank B
Document:1G5-0189
Rev.1
Page 56
VIS
Auto Precharge after Write Burst (1 of 2)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
High
t
CK2
Start Auto Precharge Bank B Start Auto Precharge Bank A Start Auto Precharge Bank B
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
RBa
RBb
RAc
A0~A9
RAa
CAa
RBa
CBa
CAb
RBb
CBb
RAc
CAc
DQM
DQ
Hi-Z
DAa0 DAa1 DAa2 DAa3 DBa0 DBa1 DBa2 DBa3 DAb0 DAb1 DAb2 DAb3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DAc2 DAc3
Activate Write Write with Activate Command Command Command Auto Precharge Command Bank A Bank B Bank A Bank B
Activate Write with Activate Command Auto Precharge Command Bank A Command Bank B Write with Bank A Write with Auto Precharge Auto Precharge Bank A Command Bank B
Start Auto Precharge Bank A
Document:1G5-0189
Rev.1
Page 57
VIS
Auto Precharge after Write Burst (2 of 2)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
High
t
CK3
Start Auto Precharge Bank B Start Auto Precharge Bank A Start Auto Precharge Bank B
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
RBa
RBb
A0~A9
RAa
CAa
RBa
CBa
CAb
RBb
CBb
DQM
DQ
Hi-Z
DAa0 DAa1 DAa2 DAa3 DBa0 DBa1 DBa2 DBa3 DAb0 DAb1 DAb2 DAb3 DBb0 DBb1 DBb2 DBb3
Activate Command Bank A
Activate Command Bank B Write Command Bank A
Write with Auto Precharge Command Bank B
Write with Auto Precharge Command Bank A
Activate Command Bank B
Write with Auto precharge Command Bank B
Document:1G5-0189
Rev.1
Page 58
VIS
Full Page Read Cycle (1 of 2)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
High
t CK2
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
RBa
RBb
A0~A9
RAa
CAa
RBa
CBa
RBb
DQM DQ
Hi-Z
QAa QAa+1 QAa+2 QAa-2 QAa-1 QAa QAa+1 QBa QBa+1 QBa+2 QBa+3 QBa+4 QBa+51QBa+6
t RP
Activate Command Bank A
Read Command Bank A
Activate Command Bank B
Read Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval
Full page burst operation does not terminate when the burst length is satisfied; the burst counter increases and continues bursting beginning with the starting address
Precharge Command Bank B Burst Stop Command
Activate Command Bank B
Document:1G5-0189
Rev.1
Page 59
VIS
Full Page Read Cycle (2 of 2)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=Full Page, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
High
t CK3
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
RBa
RBb
A0~A9
RAa
CAa
RBa
CBa
RBb
DQM DQ
Hi-Z
QAa QAa+1 QAa+2 QAa-2 QAa-1 QAa QAa+1 QBa0
t RP
QBa+1 QBa+2 QBa+3 QBa+4 QBa+5
Activate Command Bank A
Read Command Bank A
Activate Command Bank B
Read Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval
Full page burst operation does not teminate when the burst length is satisfied; the burst counter increases and continues bursting beginning with the starting address
Precharge Command Bank B Burst Stop Command
Activate Command Bank B
Document:1G5-0189
Rev.1
Page 60
VIS
Full Page Write Cycle (1 of 2)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
High
t CK2
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
RBa
RBb
A0~A9
RAa
CAa
RBa
CBa
RBb
DQM DQ
Hi-Z
DAa DAa+1 DAa+2 DAa+3 DAa-1 DAa DAa+1 DBa DBa+1 DBa+2 DBa+3 DBa+4 DBa+5 DBa+6
t
BDL
Activate Command Bank A
Write Command Bank A
Activate Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval
Write Command Bank B
Data is ignored Precharge Command Bank B Burst Stop Command
Activate Command Bank B
Full page burst operation does not terminate when the burst length is satisfied; the burst counter increases and continues bursting beginning with the starting address
Document:1G5-0189
Rev.1
Page 61
VIS
Full Page Write Cycle (2 of 2)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=Full Page, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
High
t CK3
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
RBa
RBb
A0~A9
RAa
CAa
RBa
CBa
RBb
DQM DQ
Hi-Z
DAa DAa+1 DAa+2 DAa+3 DAa-1 DAa DAa+1 DBa
tBDL
DBa+1 DBa+2 DBa+3 DBa+4 DBa+5
Data is ignored.
Activate Command Bank A
Write Command Bank A
Activate Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval
Write Command Bank B Full page burst operation does not terminate when the burst length is satisfied; the burst counter increases and continues bursting beginning with the starting address
Precharge Command Bank B Burst Stop Command
Activate Command Bank B
Document:1G5-0189
Rev.1
Page 62
VIS
Byte Write Operation
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
High
t CK2
CKE CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
CAa
CAb
CAz
LDQM
UDQM
Hi-Z
DQ0~DQ7
Hi-Z
DQ8~DQ15
Activate Command Bank A
Read Command Bank A
Upper Byte is masked
Lower Byte is masked
Write Command Bank A
Read Write Upper Command is masked Bank A
Lower Byte is masked
Lower Byte is masked
Document:1G5-0189
Rev.1
Page 63
VIS
Burst Read and Single Write Operation
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
High
t CK2
CKE CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
CAa
CAb
CAc
CAd
CAe
LDQM
UDQM
Hi-Z
DQ0~DQ7
Hi-Z
DQ8~DQ15
Activate Command Bank A
Read Command Bank A
Read Single Write Single Write Command Command Command Bank A Bank A Bank A
Lower Byte is masked Upper Byte is masked
Single Write Command Bank A
Lower Byte is masked
Document:1G5-0189
Rev.1
Page 64
VIS
Full Page Random Column Read
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
RBa
RBb
A0~A9
RAa
RBa
CAa
CBa
CAb
CBb
CAc
CBc
RBb
t RP
DQM
DQ
Hi-Z
QAa0 QBa0 QAb0 QAb1 QBb0 QBb1 QAc0 QAc1 QAc2 QBc0 QBc1 QBc2
Activate Command Bank A
Activate Command Bank B
Read Command Bank B Read Command Bank A
Read Command Bank B
Read Command Bank A
Read Command Bank B
Precharge Command Bank B (Precharge Termination) Activate Command Bank B
Read Command Bank A
Document:1G5-0189
Rev.1
Page 65
VIS
Full Page Random Column Write
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
RBa
RBb
A0~A9
RAa
RBa
CAa
CBa
CAb
CBb
CAc
CBc
RBb
t RP
DQM
DQ
Hi-Z
QAa0 QBa0 QAb0 QAb1 QBb0 QBb1 QAc0 QAc1 QAc2 QBc0 QBc1 QBc2
Activate Command Bank A
Activate Command Bank B
Write Command Bank B Write Command Bank A
Write Command Bank B
Write Command Bank A
Write Command Bank B
Precharge Command Bank B (Precharge Termination) Write Data is masked Activate Command Bank B
Write Command Bank A
Document:1G5-0189
Rev.1
Page 66
VIS
Precharge Termination of a Burst (1 of 2)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=4,8 or Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
High
t CK2
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
RAb
RAc
A0~A9
RAa
CAa
RAb
CAb
RAc
CAc
t
DPL
t
RP
t
RP
t
RP
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 Da3 QAb0 QAb1 QAb2 QAc0 QAc1 QAc2
Activate Command Bank A
Write Command Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
Precharge Command Bank A
Precharge Termination of a Write Burst. Write data is masked.
Precharge Termination of a Read Burst.
Document:1G5-0189
Rev.1
Page 67
VIS
Precharge Termination of a Burst (2 of 2)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Burst Length=4,8 or Full Page, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
High
t CK3
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
RAb
RAc
A0~A9
RAa
CAa
RAb
CAb
RAc
t DPL
t
RP
t
RAS
t
RP
DQM
t
RCD
DQ
Hi-Z
DAa0 DAa1 QAb0 QAb1 QAb2 QAb3
Activate Command Bank A
Write Command Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
Activate Command Bank A
Activate Command Bank A
Write Data is masked
Precharge Termination of a Write Burst.
Precharge Termination of a Read Burst.
Document:1G5-0189
Rev.1
Page 68
VIS
Ordering information Part Number VG3617161ET-6 VG3617161ET-7 VG3617161ET-8 VG3617161ET- 6 * VG
* 36 * 17161 *E *T *6
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Frequency@CL3 166MHz 143MHz 125MHz
Package 400mil 50-Pin Plastic TSOPII
* VIS Memory Product * Technology/Design Rule * Device Type/Configuration * Mask/Design Version * Package Type, T: TSOP * Cycle time, 6: 6ns, 7: 7ns, 8: 8ns
Packaging Information
* 400mil, 50-Pin Plastic TSOP
DIM A A1 A2 b b1 c c1 D ZD e E E1 L R R1
MIN. --0.05 0.95 0.30 0.30 0.12 0.11 20.82
MILLIMETERS NOM. MAX. ----1.00 --------20.95 0.875 REF. 1.20 0.15 1.05 0.45 0.40 0.21 0.16 21.08
MIN. --0.002 0.037 0.012 0.012 0.005 0.0045 0.820
INCHES NOM. ----0.039 --------0.825
MAX. 0.047 0.006 0.041 0.018 0.016 0.008 0.006 0.830
50
26
A2
RAD R1 RAD R
B
E1 A1 L
c
B
0~5
DETAIL A
b
0.0344 REF. 0.0315 BASIC 0.455 0.463 0.471 0.395 0.016 0.004 0.004 0.400 0.020 ----0.405 0.024 0.010 ---
0.80 BASIC 11.56 11.76 11.96 10.03 0.40 0.11 0.11 10.16 0.50 ----10.29 0.60 0.25 ---
1
D
25
b1
SECTION B-B
c1 c BASE METAL
WITH PLATING DETAIL A
NOTE: 1. CONTROLLING DIMENSION : MILLIMETERS 2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15mm(0.006") PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION. INTERLEAD PROTRUSION SHALL NOT EXCEED 0.25mm(0.01") PER SIDE. b 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONS/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD TO BE WIDER THAN THE MAX b DIMENSION BY MORE THAN 0.13mm. DAMBAR INTRUSION SHALL NOT CAUSE THE LEAD TO BE NARROWER THAN THE MIN b DIMENSION BY MORE THAN 0.07mm.
ZD
A 48- e SEATING PLANE 0.100(0.004) E
Document:1G5-0189
Rev.1
Page 69

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